In the production of an insulated gate field effect transistor memory of the type described in U.S. Pat. No. 3,508,211 and comprised of metal nitride oxide semiconductor (MNOS) memory devices having gate structures similar to that described in U.S. Pat. No. 3,590,337, a thick film field insulator is grown over a silicon substrate containing doped source and drain regions, using a process similar to that described in U.S. Pat. No. 3,573,096. The field insulator serves to electrically isolate the conductive paths of the MOS structure from the doped regions and to minimize the parasitic capacitance, therefore requiring the selection of a material of an appropriate dielectric constant and thickness to achieve this result. Using a thick field insulator in excess 1 micron reduces the parasitic capacitance in devices requiring large gate turn on voltages, but at the same time makes it more difficult to etch the necessary openings in the insulator to enable the interconnections to the source and drain regions and the formation of the appropriate gate structure.
Using thick films of silicon-oxy-nitride as the field insulator produces the above difficulties in that it becomes very difficult to etch clean, well defined openings. The difficulty arises in that the thick films require long etch times, and commonly used etch masks will not hold up over these prolonged periods. The use of standard photo-resist techniques require repeated rebaking steps, as the photo-resist tends to float away, and attempts at using aluminum etch masks have resulted in sporadic early deterioration of the mask. Attempts have also been made to combine an aluminum mask with a partial dry plasma etch before completing the etch with a wet etch, but undesirable charge accumulates at the walls of the gate openings, which charge adversely affects the electrical characteristics of the array.
To overcome these problems, it has been determined that a polycrystalline silicon etch mask can be grown over the silicon-oxy-nitride field insulator. The use of such a mask requires additional process steps but is advantageous in that the etch rate of the polysilicon mask is significantly lower than that of the field insulator, the mask can be laid down sequentially or in situ with the insulator and the crystalline structures of the insulator and mask are sufficiently compatible so that the mask won't float away over the prolonged etch periods.
While the use of a polysilicon mask requires the additional process steps of the preparation of the mask, the oxidizing of the polysilicon mask after the etch period and stripping the oxide to remove the mask, this additional thermal oxidation serves to clean the interconnect openings and the gate opening by removing the exposed portion of the substrate, which contains defects such as scar, crack, distortion and dislocation that occur at the substrate-insulator interface during the growth of the insulator. This cleaning tends to minimize pinholes in the subsequently grown gate oxide, in the manner as taught by Katajima, et al, in U.S. Pat. No. 4,039,358.
Polysilicon films have been used in the prior art as electrical interconnects, diffusion masks, ion implant masks and self aligning acid etch masks, but the inclusion of a polysilicon mask in a MOS process as an acid etch mask for etching the thick field insulator of the MOS structure is unique.
Reference is called to U.S. Pat. No. 3,475,234 issued to R. E. Kerwin, et al, where a method for making MIS structures is disclosed that teaches the use of a polysilicon film 16 as a gate electrode and as an acid etch mask in a self limiting etch technique based on the use of a differential etchant. The polysilicon 16 is used to form the self aligned gate structure 17 and to locate the gate structure 17 in the central position of the channel by overcoming any misalignment that occurs during the photo-resist mask Step 7 of FIG. 2. The polysilicon 16 is then used in steps 9 and 10 as an acid etch mask for sequentially etching layers 14 and 13 to form the complete gate structure 17. It is to be noted however, that in Step 8, where the polysilicon 16 acts as an acid etch mask for overcoming the misalignment of photo-resist mask from Step 7, the acid etch of the 0.multidot.2 micron field insulator 15 in Step 8 does produce a result similar to that described in the present invention. The principal use of the polysilicon 16 is to form a mask for defining the source, drain and gate areas, but it can be used to correct for any misalignment that might occur in Step 7. The use of the polysilicon for the corrective etching of the field insulator 15 is advantageous, but it is to be recognized that in Steps 4 and 5, where the field insulator 15 is initially etched to produce the gate opening, a standard photo-resist masking operation is used rather than the polysilicon masking procedure disclosed by the present invention. The method and structure disclosed by Kerwin would therefore have the same etching difficulties, which are removed by the present invention, especially if the field insulator 15 thickness were increased to the suggested 4 to 5 microns. The use of a polysilicon acid etch mask in the manner described hereinafter further produces openings in the field insulator of improved quality and with greater yields.